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ATmega128
Timer/Counter1
Control Register B –
Bit
7
6
5
4
3
2
1
0
TCCR1B
Read/ W rite
Initial Value
ICNC1
R/ W
0
ICES1
R/ W
0
–
R
0
WGM13
R/ W
0
WGM12
R/ W
0
CS12
R/ W
0
CS11
R/ W
0
CS10
R/ W
0
TCCR1B
Timer/Counter3
Control Register B –
Bit
7
6
5
4
3
2
1
0
TCCR3B
Read/ W rite
Initial Value
ICNC3
R/ W
0
ICES3
R/ W
0
–
R
0
WGM33
R/ W
0
WGM32
R/ W
0
CS32
R/ W
0
CS31
R/ W
0
CS30
R/ W
0
TCCR3B
? Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. W hen the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
? Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. W hen the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
W hen a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
W hen the ICRn is used as TOP value (see description of the W GMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap-
ture function is disabled.
? Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
? Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
? Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure
55 and Figure 56 .
135
2467X–AVR–06/11
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